Exemplary embodiments relate to a semiconductor device and a method of manufacturing the same and, more particularly, to a non-volatile memory device having a three dimensional (3-D) structure and a method of manufacturing the same.
A non-volatile memory device retains its data even after a power supply is cut off. As the degree of integration of two dimensional (2-D) memory devices fabricated over a silicon substrate as a single layer in reaching physical limits, a 3-D non-volatile memory device in which memory cells are vertically stacked from a silicon substrate is being developed.
A conventional method of manufacturing a 3-D non-volatile memory device and features thereof are described below with reference to the accompanying drawings.
FIGS. 1A to 1E are cross-sectional views illustrating a conventional process of manufacturing a non-volatile memory device having a 3-D structure. For illustration purposes, while a memory cell region is not depicted, pad regions are shown.
As shown in FIG. 1A, a plurality of interlayer dielectric layers 11, 13, 15, 17, and 19 and a plurality of conductive layers 12, 14, 16, and 18 are alternately formed over a substrate (not shown) which has cell region and pad region.
A process for forming channels extending from the substrate and a plurality of memory cells stacked along the channels is performed, while a detailed description thereof is omitted as being well-known.
Subsequently, a photoresist pattern 20 for forming pad regions is formed over the plurality of interlayer dielectric layers 11, 13, 15, 17, and 19 and the plurality of conductive layers 12, 14, 16, and 18.
The photoresist pattern 20 is used as an etch barrier in an etch process of forming pad regions to be coupled to contact plugs for a plurality of word lines. The width W of the photoresist pattern 20 first formed is set so as to expose the pad region of the lowest conductive layer 12.
Subsequently, the highest interlayer dielectric layer 19 and the highest conductive layer 18 are etched using the photoresist pattern 20 as an etch barrier.
As shown in FIG. 1B, the photoresist pattern 20 corresponding to the width of the pad region is removed by etching. Subsequently, the highest interlayer dielectric layer 19 and the highest conductive layer 18 are etched using the remaining photoresist pattern 20A as an etch barrier. In the process of etching the highest interlayer dielectric layer 19 and the highest conductive layer 18, a step between layers as formed by etched photoresist pattern 20B is also transferred to the etched layers below. Further, the interlayer dielectric layer 17 and the conductive layer 16 under the highest interlayer dielectric layer 19 and the highest conductive layer 18 are etched.
In FIG. 1B, the etched interlayer dielectric layers are assigned reference characters 19A and 17A, and the etched conductive layers are assigned reference characters 18A and 16A.
As shown in FIG. 1C, the photoresist pattern 20A is etched to be partially removed by a length equal to the width of the pad region. Subsequently, the interlayer dielectric layers 19A, 17A, and 15, exposed by the shortened photoresist pattern 20B are etched. Further, the conductive layers 18A, 16A, and 14 under the interlayer dielectric layers 19A, 17A, and 15 are etched.
In FIG. 1C, the etched interlayer dielectric layers are assigned reference characters 19B, 17B, and 15A, and the etched conductive layers are assigned reference characters 18B, 16B, and 14A.
As shown in FIG. 1D, the photoresist pattern 20B is etched to be partially removed by a length equal to the width of the pad region. Subsequently, the interlayer dielectric layers 19B, 17B, 15A, and 13, exposed by the shortened photoresist pattern 20C, and the conductive layers 18B, 16B, 14A, and 12 under the interlayer dielectric layer 19B, 17B, 15A, and 13 are etched.
In FIG. 1D, the etched interlayer dielectric layers are assigned reference characters 19C, 17C, 15B, and 13A, and the etched conductive layers are assigned reference characters 18C, 16C, 14B, and 12A.
Accordingly, the plurality of interlayer dielectric layers 19C, 17C, 15B, and 13A and the plurality of conductive layers 18C, 16C, 14B, and 12A form a stepwise pattern so that the surface of each of the plurality of conductive layers is exposed, where the exposed regions of the conductive layers form pad regions for the plurality of conductive layers 18C, 16C, 14B, and 12A.
As shown in FIG. 1E, an insulating layer (not shown) is formed on the entire structure of the resulting structure in which the pad regions are formed as described above. Subsequently, contact holes through which the respective pad regions of the plurality of conductive layers 18C, 16C, 14B, and 12A are exposed are formed.
A conductive layer is buried in the contact holes to form a plurality of contact plugs 21 coupled to the respective conductive layers 18C, 16C, 14B, and 12A.
The above-described conventional process, however, has a feature where neighboring word lines are bridged or circuits are disconnected when the pad region and the contact plug are misaligned (refer to I in FIG. 1E). Such a feature is described in detail below.
In the conventional art, the conductive layers 18C, 16C, 14B, 12A are made to have the pad regions having the same width by repeatedly performing an etch process while shortening the photoresist pattern by a same width each time. Here, the shortening of the photoresist pattern by a uniform length may be difficult to perform. Furthermore, if an error is generated, the errors are accumulated in the process of repeatedly performing the etch process. Accordingly, an error in the position and width of the pad region is increased for the conductive layer placed higher, where a probability that the contact plugs are misaligned is increased for the conductive layers that are located at higher positions.
To address such features, a method of securing a misalignment margin by generally increasing the width of the pad region has been used. In increasing the width of the pad region, the overall cell area is increased. Here, the thickness of the photoresist pattern is also decreased in the process of shortening the photoresist pattern. Thus, with an increase in the width of the pad region, a reduction in the thickness of the photoresist pattern is also increased. Consequently, the highest word line may be damaged when the photoresist pattern is fully removed in the process of repeatedly performing the etch process.